Scan testing is an important tool for efficient development and production testing of complex integrated circuits, such as systems-on-a-chip (SOCs). Generally, scan cells, which typically are one-bit register elements, are associated with test critical I/O nodes of a given functional circuit block. The scan cells of one or more circuit blocks are connected in serial to form a scan chain (shift register). During normal functional operations of the system, the scan cells behave like traditional register elements; however, during test operations, a test vector is shifted into the scan chain in response to a clock and the individual bits presented in parallel at the functional circuit input nodes. During a subsequent capture operation, the resulting bits at the corresponding output of the functional circuitry nodes are clocked in parallel into the scan cells. Multiple capture operations are possible, depending on the tests being performed. The resulting vector is then shifted out of the scan chain for observation and analysis.
Implementing scan testing in an SOC with multiple functional blocks operating from multiple clock domains and sub-domains is a formidable challenge, particularly when thousands of scan cells in multiple-scan chains are required to implement a thorough test protocol. Among the problems faced is reconciling differences between the clock domains/sub-domains during scan testing such that the system can be tested synchronously. Additionally, the order and reordering of the scan cells in a given scan chain, as well as selecting the appropriate insertion points, should be optimized for physical layout and test operational efficiency.
Specifically, in conventional scan testing schemes, the functional clocks which drive the associated functional circuitry are also used to generate the clocks used to scan and capture data in the scan chain. Normally, all cells in a given clock domain should be contiguous and therefore lockup latches are provided in the scan chain when that scan chain crosses clock domain boundaries. In turn, it becomes difficult to form scan chains which have optimal physical lay out on the chip or which optimally exercise interrelated functional blocks.
Another problem is clock skew between the various clocks being used to shift and capture data across the design in the scan chains. Clock skew, which is typically caused by propagation delays through the clock lines, can result in data “shoot-through” where data bits are not clocked into the proper scan cells during shifting and capture operations. Moreover, it becomes difficult to build scan chains when multiple clock domains are being utilized on chip and/or when functionally connected cells are not operating from the same clock branch.